1. Field of the Invention
The present invention relates to a ceramic multilayer wiring substrate including a via conductor disposed therein and a module in which a component is mounted on the ceramic multilayer wiring substrate.
2. Description of the Related Art
As illustrated in FIG. 7, a module in which a component, such as an integrated circuit (IC), is flip-chip mounted on one main surface of a ceramic multilayer wiring substrate is currently known (see Japanese Unexamined Patent Application Publication No. 2005-191134, particularly, paragraphs [0036] and [0037], FIG. 1, and other portions). The module 100 includes a ceramic multilayer wiring substrate 101 and a component 103, such as an IC. The ceramic multilayer wiring substrate 101 is a multilayer body that includes laminated ceramic insulating layers 101a each including a surface on which a wiring pattern 102 is formed. The component 103 is flip-chip mounted on a first main surface of the ceramic multilayer wiring substrate 101. In addition, multiple mounting terminals 106a to 106e for allowing the component 103 to be mounted thereon are formed on the first main surface of the ceramic multilayer wiring substrate 101 while multiple external electrodes 105 for connection to external devices are formed on a second main surface of the ceramic multilayer wiring substrate 101. Inside the ceramic multilayer wiring substrate 101, multiple via conductors 104 are formed so as to connect wiring patterns 102 of different ceramic insulating layers 101a together.
A ceramic multilayer wiring substrate, such as the ceramic multilayer wiring substrate 101, is typically formed in the following manner. Firstly, multiple ceramic green sheets are prepared by forming sheets from a slurry, which is a mixture of materials, such as alumina and glass, in powder form, an organic binder, a solvent, and other components, and then forming via holes at predetermined positions of the ceramic green sheets by a method, such as laser processing. Subsequently, the via holes are filled with a conductor paste containing materials, such as Ag or Cu, to form via conductors 104 for interlayer connection and various wiring patterns 102 are printed on the sheets with the conductor paste. Thereafter, the ceramic green sheets are laminated together into a multilayer body and the multilayer body is pressed at a predetermined pressure and fired at a predetermined temperature to fabricate a ceramic multilayer wiring substrate 101.
Here, the ceramic green sheets and the via conductors 104 have different heat shrinking characteristics. For example, when the above-described multilayer body is fired, the thickness of the ceramic multilayer wiring substrate 101 may vary between the areas in which the via conductors 104 are disposed and the areas in which the via conductors 104 are not disposed when the ceramic multilayer wiring substrate 101 is viewed in a plan. Specifically, the ceramic green sheets have a higher shrinking characteristic than the via conductors 104. Thus, the sheets have a smaller thickness in the areas in which the via conductors 104 are not disposed than in the areas in which the via conductors 104 are disposed. The areas on the top surface of the ceramic multilayer wiring substrate 101 in which the via conductors 104 are disposed when viewed in a plan consequently rise. The amount by which the areas rise increases as the total length of the via conductors 104 disposed in the areas of the top surface when viewed in a plan increases.
In the existing module 100 illustrated in FIG. 7, the total length of the via conductors 104 disposed below the mounting terminal 106a (see the arrow a) at the middle among the mounting terminals 106a to 106e is longer than the total length of the via conductors 104 disposed below each of the other mounting terminals 106b to 106e (see the arrows b to e). Thus, if the ceramic multilayer wiring substrate 101 is fabricated by the above-described typical method, the middle mounting terminal 106a has a height in the stacking direction greater than heights of the other mounting terminals 106b to 106e. When, as in the above-described case, the mounting terminals 106a to 106e are not positioned on the same plane, the component 103 may be defectively mounted on the ceramic multilayer wiring substrate 101, the component 103 mounted on the ceramic multilayer wiring substrate 101 may become unstable and misaligned at the time of connection, or some of the mounting terminals 106a to 106e and the corresponding terminals of the component 103 may fail to be connected due to poor solder wettability.